IC/LSI Engineering Shuttle Services

As a design house, Steady Design understands the importance of keeping up with budget and deadline and the need for more available prcesses when it comes to IC design. Our shuttle service provides a perfect solution for maximizing the use of resources and budget. We offer frequent shuttle services using mainly TSMC standard processes. Chip assembly, testing, failure analysis and many other options are also available. Since the service was lauched in 2004, up till the end of 2012, Steady had successfully supported the development of 107 sets of masks and 499 chips.

Our Features

  • Many different types of processes are available
  • Greatly cuts down the time and cost for engineering run
  • Many accessable data library are available
  • Can also provdie design varification services
  • Assembly, CP, FT test, failure analysis and many other options to choose from
  • Smooth transition to mass production stage

shuttleOffer process

The following are proven processes, we can also support other processes.
If you need shuttle schedule, feel free to contact us.  shuttle@steady.co.jp

Offer process
TSMC 0.50um 5/40V CMOS
0.18um CMOS Image Sensor/Mix Mode
Macronix 1 um 700V CDMOS
0.5 um 5/18V BCDMOS
0.5 um 5/33V BCDMOS
0.5 um 5/65V BCDMOS
0.35um 3.3/5V CMOS
シャトルスケジュール（外部リンク）
XFAB 1um 700V CDMOS
0.6um 60V CDMOS
SMIC 0.35um 3.3/5V CMOS/BiCMOS
0.35um 3.3/5/18/24/30V BCD
TowerJazz 0.18um CMOS Image Sensor/SL
0.18um 1.8V/3.3V CMOS
External links for Shuttle schedule
UMC 0.35um 5V CMOS
0.35um 5/40V CDMOS
Additionally, MEMS foundry can be used.

Process Flow

  1. Signing the NDA

    2. To ensure information confidenciality amoung our client, Steady Design and our fabs, signing the NDA is required for the use of our shuttle services. For more information regarding the NDA, please send inquiries to shuttle@steady.co.jp

  2. Making a Reservation

    3. Please provide us with basic information such as preliminary data submission schedule and the process required. Reservation is free of charge and must be confirmed 7 days before data submission deadline. Any cancellation after the deadline is subject to a cancellation charge.

  3. Design Process

    4. Circuit design should follow the information provided by Steady Design.We also offer design consulation.

  4. Tape Out

    5. Baisc data such as mask data (GDS, CIF), process option and bonding diagram (if assembly is required) are required for submission.

  5. Mask Production and Wafer Process

    6. Lead time may vary depending on the type of process and the option chosen (need 8 weeks to complete on the average).Please feel free to contact us.

  6. Dicing and Assembly

    7. After dicing, chips can be shipped out as bare chips on chiptrays. Packaging and assemebly services are also available.